Autores: O. Lifschitz, J. A. RodrÃguez, P. Julián, O. Agamennoni
Instituciones:
Instituto de Investigaciones en IngenierÃa Eléctrica – IIIE (UNS-CONICET)
Departamento de IngenierÃa Eléctrica y de Computadoras – Universidad Nacional del Sur
Resumen:
In this paper, we present the environment set for validation and testing a particular ASIC that implements a piecewise linear (PWL) architecture. Description for a package debug propose is included. Methodologies for power consumption and envelope and maximum operation frequency estimation, based on laboratory measurements, are described.
