Post-silicon Validation Procedure for a PWL ASIC Microprocessor Architecture

Autores: O. Lifschitz, J. A. Rodr铆guez, P. Juli谩n, O. Agamennoni
Instituciones:
Instituto de Investigaciones en Ingenier铆a El茅ctrica – IIIE (UNS-CONICET)
Departamento de Ingenier铆a El茅ctrica y de Computadoras – Universidad Nacional del Sur

Resumen:
In this paper, we present the environment set for validation and testing a particular ASIC that implements a piecewise linear (PWL) architecture. Description for a package debug propose is included. Methodologies for power consumption and envelope and maximum operation frequency estimation, based on laboratory measurements, are described.

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